# Physical Design Engineer

**Company:** [Weekday AI](http://jobs.workable.com/companies/pxG9rDgnvZm2c86JUchT1j.md)
**Location:** Bengaluru, India
**Workplace:** on site
**Employment type:** Full-time
**Department:** Weekday's Client via platform

[Apply for this job](http://jobs.workable.com/view/b5a425b6-9fec-4fac-b98a-1a7006107e96)

## Description

**This role is for one of Weekday’s clients  
Salary range: Rs 3000000 - Rs 7500000 (ie INR 30 - 75 LPA)**

Min Experience: 6+ years

Location: Bengaluru  
JobType: full-time

We are seeking an experienced **Physical Design Engineer** with **6–15 years of industry experience** to join our VLSI/ASIC engineering team. The ideal candidate will have strong hands-on expertise across the physical implementation flow, with particular emphasis on **Cadence Innovus** and **Static Timing Analysis (STA)**. You will be responsible for taking designs from netlist through physical implementation, optimization, timing closure, and sign-off while working closely with RTL, synthesis, STA, and verification teams.

## Requirements

### Key Responsibilities

-   Perform end-to-end physical design activities including **floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and physical verification**.
-   Develop and implement physical design strategies for complex digital blocks and full-chip designs.
-   Use **Cadence Innovus** extensively for placement, CTS, routing, timing optimization, and design closure.
-   Analyze timing reports and perform **STA** to identify setup and hold violations and drive timing closure.
-   Work on congestion analysis, placement optimization, buffering, cell sizing, and other techniques to improve PPA and timing.
-   Perform clock-tree analysis and optimization to manage skew, latency, transition, and clock-related constraints.
-   Collaborate with synthesis and RTL teams to resolve timing, area, power, and physical-design challenges.
-   Debug implementation issues and develop effective solutions to achieve design goals within schedule and PPA constraints.
-   Review and validate design constraints, timing exceptions, clock definitions, and implementation quality.
-   Support physical sign-off activities and ensure designs meet required performance, power, and reliability targets.
-   Participate in methodology improvements, automation, flow development, and physical design optimization initiatives.

### Must-Have Skills

-   **6–15 years of hands-on experience in Physical Design / ASIC implementation.**
-   Strong expertise in **Cadence Innovus** and experience using it across the physical implementation flow.
-   Strong understanding and practical experience with **Static Timing Analysis (STA)** and timing closure.
-   Solid knowledge of the complete physical design flow from **netlist to GDSII**.
-   Strong understanding of floorplanning, power planning, placement, CTS, routing, optimization, and physical verification.
-   Experience debugging setup/hold violations and resolving timing and congestion issues.
-   Good understanding of multi-mode, multi-corner (MMMC) implementation and timing constraints.
-   Familiarity with physical design challenges related to advanced semiconductor process nodes.
-   Strong scripting/automation skills using **Tcl, Python, or Shell** are desirable for flow automation and analysis.

### Good-to-Have Skills

-   Experience with **EMIR (Electromigration and IR Drop) analysis** and power integrity considerations.
-   Exposure to IR-drop analysis, electromigration checks, and power-grid optimization.
-   Experience working with physical sign-off tools and methodologies.
-   Knowledge of industry-standard physical verification and sign-off flows.
-   Experience with low-power design methodologies and power optimization.
-   Exposure to advanced-node designs and complex SoC implementation.

### Education

Bachelor’s or Master’s degree in **Electronics Engineering, Electrical Engineering, VLSI, Microelectronics, or a related discipline**.