# Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)

**Company:** [Erbity Private Limited](http://jobs.workable.com/companies/ofZNxaSYsQxnso7LN4hhk2.md)
**Location:** Hyderabad, India
**Workplace:** hybrid
**Employment type:** Full-time
**Department:** Verification Engineering

[Apply for this job](http://jobs.workable.com/view/d54571c1-83a5-44d3-a096-5cc027eb4588)

## Description

If breaking designs before tapeout sounds fun, you’re exactly who this is for.

-   4–6 years in IP/Block/Subsystem verification
-   Strong expertise in SystemVerilog and UVM methodology
-   Experience building test plans, environments, and testbenches
-   Strong RTL debugging, assertions, and coverage analysis
-   Knowledge of AXI/AHB and protocols like DDR, PCIe, NVMe
-   Experience in end-to-end verification from plan to signoff
-   Exposure to mentoring and working in global teams
-   Strong communication and problem-solving skills

If you believe first-pass silicon is discipline, not luck, let’s connect.

## Requirements

Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)

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